Scan test pattern sets typically consist of several thousand individual “load/unload” patterns, where each pattern consists of serially inputting a unique test stimulus data state into each flipflop in the IC.
It is often the case that test engineers program Automatic Test Equipment (ATE) to record each failure in a test pattern set to determine which flipflop and which pattern the failure was observed on. This data can be used by subsequent offline analysis tools.
As an example consider the case:                2,000 flipflops in a scan chain        10,000 patterns applied        A single fault exists in the IC which may affect 4 flipflops (depending on the pattern)        Total # of vectors applied in the test pattern set=20,000,000.        Number of failing vectors=12,000 (0.30% of patterns×4 flip-flops)        
This number increases proportionally with the # of faults in an IC.
Most semiconductor IC testers may have an “Error Capture Memory” of a specific capacity. The size of this memory can vary significantly with different tester models (e.g. 1,024 locations to 32 million locations)
In a conventional tester, as illustrated in FIG. 6, data is written into a memory location only when a failing cycle is detected. This requires that a cycle number be also recorded into the memory along with the pin Pass/Fail data as can be observed in FIG. 7.
If the memory is not large enough to accommodate all the failures that occur in a single pattern set, the test pattern set may be repeated several times with the memory reconfigured to capture a different sequence of failing vectors each pass. One method for doing this is to have a “hold-off” counter which can be initialized to ignore the first “n” failing cycles.
Transferring the error capture memory contents back to the tester CPU, and subsequently into a disc file for off-line analysis, is a time consuming task which can have a negative impact on throughput in a semiconductor manufacturing test environment
Furthermore, it may be wasteful because there are applications in which it is only useful to determine which flipflops failed and unnecessary to know the individual pattern which detected a failure.
There are certain applications in which it is only desired to determine which “additional” flipflops failed in a specific pattern set execution while ignoring flipflops that failed in any previously executed test pattern sets.
There are applications in which the number of failures recorded in a single test pattern set is too large to be handled by conventional testers. One example of these applications is a “frequency” search which is intended to determine the maximum passing frequency of each flipflop. This is accomplished by repetitive re-executions of a scan test pattern set while incrementing the test frequency at each step and recording at what frequency each flipflop first fails at. The table in FIG. 8 exemplifies the benefit this invention provides by comparing the amount of data that must be logged, retrieved from error capture memory, and processed by software to accomplish this process in a conventional tester and in a tester equipped with the present invention.
Test Case: A flipflop fails 25% of the patterns when above its maximum frequency.                100,000 total scan cells (50 chains of 2,000 scan cells each)        5,000 scan load/unload patterns        
Thus it can be appreciated that what is needed is an apparatus which can efficiently compress failure data logs on a tester to reduce the storage and data transfer for test pattern failures.